Cyber On Board Presentation

30 Apr 2025
event, cybersecurity, embedded AI

The second edition of the conference dedicated to the cybersecurity of embedded systems and its ecosystem will take place from 13 to 15 May on the Giens peninsula.

Our PhD student, Pierre Garreau, will be presenting his work on the hardware security of embedded AI with a talk entitled :

Hardware support for the distribution of embedded AI engines

In recent years, the use of unmanned aerial vehicles (UAVs) in packs has developed significantly, offering numerous advantages such as improved performance thanks to the division of tasks, greater scalability and increased robustness. The ability to combine multiple environments (air, land, sea, underwater) extends their field of action, at the cost of greater complexity. Unmanned aerial vehicles (UAVs) are both mobile and communication-limited (range, throughput), particularly for reasons of stealth or environment. The first consequence is the highly dynamic topology of the packs, which deprives them of the decision-making capacity that requires a global vision. A second consequence is the need for the infrastructure to be able to operate autonomously, without necessarily requiring an operator. In addition, the increasingly critical nature of the missions entrusted to these systems, and their evolution in uncertain environments (unknown, evolving, heterogeneous because multi-milieu), imposes very high levels of safety/security. It is therefore crucial to optimise the performance and resilience of drone packs in the face of potential attacks. In the upstream phase, supervised or unsupervised learning is carried out on the basis of previous recordings, which feeds into self-monitoring in the operational phase. The work presented deals with the use of artificial intelligence to detect malicious network traffic (e.g. GPS spoofing, identity corruption). These AI engines are deported in drones. As UAVs are embedded systems with limited resources (energy, storage, computing), an optimised hardware support for inference is proposed; it consists of a hardware accelerator coupled to a RISC-V processor. This support enables the implementation of multi-application strategies (intrusion or object detection, support for variable levels of accuracy, and balancing between competing tasks whose priority changes over time).

For more information : https://www.cyberonboard.org/fr