Pierre Garreau
Directeur(s): Loïc Lagadec
Encadrant(s): Pascal Cotret, Jean-Christophe Cexus & Julien Francq
AI Hardware Acceleration for IDS Applications
Intrusion Detection Systems (IDS) are increasingly incorporating Artificial Intelligence (AI) [1, 2, 3, 4]. However, to be effective in their learning or inference processes, these IDS must integrate co-processors that accelerate computations while ensuring the validity of their results. Indeed, it is preferable for a probe not to return false positives and to be resistant to model or data leaks that could compromise the training dataset.
To implement this probe and its co-processor, we aim to use the open-source RISC-V architecture [5]: this standard allows for the easy addition of specialized instructions in certain domains, such as AI. Moreover, some processors based on this RISC-V architecture natively offer an interface to add co-processors [6].
These co-processors are often referred to as TPUs (Tensor Processing Units) or NPUs (Neural Processing Units) [7] and will serve as initial approaches for developing an embedded IDS on a RISC-V processor. A demonstrator will be developed to showcase the performance of the algorithms created within the scope of this research. Furthermore, the processor must be resilient to external attacks and should not introduce vulnerabilities into the overall system.
Bibliographic References:
[1] R. Zhang, Intrusion detection in a fleet of drones. PhD thesis, Université de Toulouse, 2022. Doctoral dissertation supervised by Larrieu, Nicolas and Condomines, Jean-Philippe, Automatique et Informatique, Toulouse, ISAE, 2022.
[2] J. Whelan, A. Almehmadi, and K. El-Khatib, “Artificial intelligence for intrusion detection systems in unmanned aerial vehicles,” Computers and Electrical Engineering, vol. 99, p. 107784, 2022.
[3] Q. Liang, S. Xie, and B. Cai, “Intelligent home IoT intrusion detection system based on RISC-V,” in 2023 IEEE 3rd International Conference on Power, Electronics and Computer Applications (ICPECA), pp. 296–300, 2023.
[4] X. Tang, S. Han, L. L. Zhang, T. Cao, and Y. Liu, “To bridge neural network design and real-world performance: A behavior study for neural networks,” in Proceedings of Machine Learning and Systems (A. Smola, A. Dimakis, and I. Stoica, eds.), vol. 3, pp. 21–37, 2021.
[5] RISC-V, “The RISC-V instruction set manual - Volume I and Volume II.” https://riscv.org/technical/specifications/.
[6] OpenHW Group, “4-stage, in-order, compute RISC-V core based on the CV32E40P.” https://github.com/openhwgroup/cv32e40x.
[7] S. Kalapothas, M. Galetakis, G. Flamis, F. Plessas, and P. Kitsos, “A survey on RISC-V-based machine learning ecosystem,” Information, vol. 14, no. 2, 2023.
[8] P. Chifflier and A. Fontaine, “Secure system architecture for network IDS probes,” 2015.
[9] G. Choudhary, V. Sharma, I. You, K. Yim, I.-R. Chen, and J.-H. Cho, “Intrusion detection systems for networked unmanned aerial vehicles: A survey,” in 2018 14th International Wireless Communications & Mobile Computing Conference (IWCMC), pp. 560–565, 2018.
[10] M. E. Bouazzati, R. Tessier, P. Tanguy, and G. Gogniat, “A lightweight intrusion detection system against IoT memory corruption attacks,” in 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 118–123, 2023.
[11] Q. Ducasse, P. Cotret, and L. Lagadec, “JIT Compiler Security through Low-Cost RISC-V Extension,” in 30th Reconfigurable Architectures Workshop, (St Petersburg, Florida, United States), May 2023.
[12] Q. Ducasse, P. Cotret, L. Lagadec, and R. Stewart, “Benchmarking quantized neural networks on FPGAs with FINN,” CoRR, vol. abs/2102.01341, 2021.
